From the beginning of the integrated circuit industry, the need for resistive devices and load resistors to operate as resistive pull-up devices has existed. A resistive pull-up device is a device connected to a main power supply of a transistor circuit and is needed to achieve high and low logic voltage levels. The early needs for a resistive pull-up device where satisfied by semiconductor resistive lines such as doped substrate-contained resistors and was improved upon much later in time by polysilicon resistor layers. The devices resulting from polysilicon and silicon loads were widely used but had several disadvantages, such as: (1) a large surface area and therefore poor circuit density; (2) a large amount of power consumption; (3) slow speed of operation; (4) a high occurrence of manufacturing-related inconsistencies and variation between die to die and wafer to wafer; (5) the inability to attain the consistently decreasing new dimensions required for performance improvements; and (6) higher leakage currents and other limitations.
To improve upon performance and circuit density the industry began to research and adopt active load pull-ups which are gate biased thin-film transistors (TFTs) that act as voltage variable resistors. These gate biased TFTs provided several advantages: (1) a more power efficient replacement for resistive pull-ups, which was observed in the active load pull-up configuration in conventional complementary metal oxide semiconductor (CMOS) technology; (2) faster operational speed; (3) increased circuit density; and (4) submicron dimensional capability. As technology progressed, the TFTs used as pull-up structures developed the following limitations: (1) isolation problems such as the widely observed and understood latch-up phenomena; (2) increased leakage currents; (3) short channel behavior such as drain induced barrier lowering (DIBL) which adversely affects threshold voltages; (4) size reduction limitations; and (5) larger resistive losses. It was becoming apparent that a new technology was needed to further reduce structures beyond the conventional submicron sizes and to achieve higher levels of performance.
To achieve the new levels of performance that were needed primarily by dynamic random access memory (DRAM) devices and fast static random access memory (FSRAM) devices, the industry began to research silicon on insulator (SOI) technology. Most successful SOI technology involves the growth or deposition of a thin region of semiconductor material, such as silicon, used as an FET channel. This channel is contained by dielectrics on perimeters requiring isolation and is placed adjacent to a source region and a drain region, which is usually another conductive or semiconductive material to allow FET current flow and device operation.
One known SOI structure and process uses a substrate which comprises a gate dielectric overlying the substrate and a gate electrode contained within the substrate underlying the gate dielectric. A polysilicon layer is formed on the gate dielectric and doped to a predetermined first conductivity. A portion of the polysilicon layer overlying the gate electrode is oxidized which consumes the polysilicon over the gate electrode to a smaller thickness while keeping the surrounding polysilicon thicker. This smaller thickness now forms a transistor channel region where current will flow when the device assumes an "on" state. The thicker polysilicon surrounding the now thinner channel polysilicon region is then counterdoped to a conductivity opposite of the channel polysilicon region, thereby forming a source and a drain.
This known SOI structure helped to improve isolation and provide benefits over active pull-up resistor structures, but the structure had a few disadvantages as well. One disadvantage is that the source, drain, and channel region are formed from the same layer of polysilicon material and this layer is exposed to many changes in doping from implants, diffusions, or other methods. These methods of doping can cause an exchange or flow of dopant charge between the source and the channel, and the drain and the channel during subsequent processing steps that can produce undesirable and unpredictable shifts in device performance. The process used to form the channel region in the described SOI structure creates inconsistent channel thicknesses because oxidation resulting in silicon consumption, which is typically hard to repeat consistently, is relied on for channel formation. The channel thickness variation from die to die and wafer to wafer can cause unacceptable device performance variation. Polysilicon is also not a desirable material to choose for the source and drains due to the high temperature processing which polysilicon requires to activate electrical charge and due to other known limitations.
Several other SOI technologies having some improvements were proposed. A known and improved SOI structure comprised an SOI FET with a thicker channel region and thin source drain regions. Other research involved devices where the channel and gate were defined and etched in separate steps from the source and drain formation and usually required epitaxial growth of materials. These processes did improve performance in several areas but they still had a few disadvantages, for instance: (1) large series resistive losses; or (2) the need for high temperature processing; or (3) charge transfer phenomena that changed device performance; or (4) the processing limitations of polysilicon; or (5) poor contact metallurgy compatibility. It is therefore apparent that a process is needed to overcome these disadvantages.